This chapter explains what happens on the wires between the FPGA and the DRAM, and why a DRAM interface must be tuned at boot. It covers the signals, the strobes, the board topology, the leveling procedures, the termination and the reference voltages, then the clocks of the FPGA and the DFI interface between the controller and the PHY.
Each section ends with the part of LiteDRAM that implements the mechanism. The previous chapter, DRAM in a nutshell, explained the commands and the timings; Initialization and calibration gives the exact steps the BIOS runs.
A DRAM interface has two halves. The command and address half goes one way, from the controller to the DRAM, and is shared by every chip of a rank. The data half is bidirectional and split into byte lanes, each with its own strobe. The figure below shows the signals.
